Senior Digital Design / Architect (IP Security)

My client is a global leader in data & security, development and licensor of Semiconductor IP.

Salary = €75-95k (dependent on level of seniority), bonus, RSUs, relocation, and visa sponsorship all available.

As the Principal Engineer of Digital Design & Architecture for IP Security, you will be responsible for the design, development & architecture of embedded hardware security IP for the semiconductor industry, on a global scale.

You will be working closely with other ASIC engineers and architects, as well as security, cryptography, embedded hardware & software, firmware, and verification engineers to architect, design, implement, and integrate the latest solutions for digital hardware in the security market, including crypto and Post-Quantum cores.

Experience/Skills

• MS/PhD degree in electrical or computer engineering required, PhD preferred
• 5-10 years of professional experience of working in secure hardware / IC design, or PhD / research related study
• Design, implementation & micro-architecture of efficient cryptographic algorithms that implement side channel analysis countermeasures
• Knowledge of HW security architectures and IPs (secure MCU cores, cryptographic co-processors, secure memories, secure elements, smart cards)
• Familiarity with front-end ASIC design flows, including design, simulation, assertions, formal verification, synthesis, timing analysis, logical equivalence checking, and linting/rule checking. Experience with back-end flows, especially place-and-route, is beneficial.
• Proven track record of on-time delivery of silicon-proven designs.
• Demonstrated proficiency in Verilog and digital design.
  
  

Expertise in some or all of the following areas is a bonus:

• Secure hardware design (ASIC / FPGA)
• Definition of architecture for Security IP
• Data processing
• Cryptographic algorithms and side-channel attacks
• High performance CPU architecture and design.
• Modern SoC design methodologies and architecture
  
  

Tools/Technologies

• Verilog, SystemVerilog, Perl
• Shell scripting, Python, Sage, Tcl
• C, C++
• MATLAB, Xilinx Vivado
• Unix, Linux
• Front-end ASIC design tools - synopsys/cadence/mentor
  
  

Excellent salary, bonus, stocks/shares, visa sponsorship and relocation bonus are all available for this fantastic opportunity with a fantastic employer.

For more information please apply with your CV and request a conversation today!

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