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Senior Silicon Verification Engineer (AI Hardware) - SystemVerilog & UVM

IC Resources United Kingdom
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AI Summary

Lead the development of advanced verification environments for AI hardware, shaping scalable methodologies and automation. Collaborate with architecture, RTL, and software teams to ensure robust silicon verification using SystemVerilog, UVM, and Python. Influence verification infrastructure and workflows in a fast-growing AI hardware company.

Key Highlights
Lead verification infrastructure, automation, and methodology for AI hardware development
Develop SystemVerilog/UVM testbenches and Python-based verification automation
Work closely with architecture, RTL design, and software teams in a collaborative environment
Key Responsibilities
Develop and maintain SystemVerilog/UVM verification environments for complex AI hardware
Create reusable testbenches, verification components, and functional coverage models
Improve verification automation using Python and contribute to methodology improvements
Debug RTL issues, analyze simulation results, and collaborate with design/software teams
Shape verification infrastructure and workflows to enhance scalability and efficiency
Technical Skills Required
SystemVerilog UVM Python
Benefits & Perks
Visa sponsorship and relocation support available
Nice to Have
Experience with ASIC or SoC verification
Functional coverage and SystemVerilog Assertions (SVA) expertise
Building verification automation or improving verification environments

Job Description


Senior Silicon Verification Engineer | AI Hardware | SystemVerilog | UVM | Python

Location: Bristol or London (Hybrid)

Visa sponsorship and relocation support available

If you’re a verification engineer who’s interested in more than just writing UVM testbenches, this could be a great opportunity.

I’m working with an exciting AI hardware company that’s building next-generation compute technology. They’re looking for experienced Silicon Verification Engineers to help verify complex hardware while also shaping the verification infrastructure, automation and methodology that supports the wider engineering team.

This is a role for someone who enjoys solving problems, improving workflows and using software to make verification more scalable and efficient.

You’ll work closely with architecture, RTL design and software teams to verify complex silicon using modern verification methodologies.

Alongside developing SystemVerilog and UVM environments, you’ll also have the opportunity to build Python automation, improve verification infrastructure and influence how the team approaches verification as the company grows.

Responsibilities

  • Develop SystemVerilog/UVM verification environments
  • Create reusable testbenches and verification components
  • Develop verification plans, functional coverage and assertions
  • Debug RTL issues and analyse simulation results
  • Improve verification automation using Python
  • Contribute to verification methodology and infrastructure
  • Work closely with architecture, design and software engineers throughout the development cycle

What They’re Looking For

You’ll ideally have experience with:

  • SystemVerilog
  • UVM
  • ASIC or SoC verification
  • Functional coverage
  • SystemVerilog Assertions (SVA)
  • Python or another scripting language
  • RTL debugging

Experience building automation, improving verification environments or contributing to verification methodology would be a real advantage.

Why join?

This is an opportunity to have a genuine influence on how verification is done, rather than simply maintaining existing environments.

You’ll work on challenging AI hardware alongside experienced engineers in a collaborative environment where good ideas are valued, and where verification is seen as a key part of product development.

If you’re looking for a role where you can combine strong verification skills with software and automation, I’d be happy to tell you more contact Steph Hutchinson.

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