STA Engineer

AUTSORSA is a fast-growing company founded and based in Bulgaria that serves clients from all over the world, providing business outsourcing, outstaffing and HR services.

Our client is a leading European semiconductor company developing cutting-edge AI chip infrastructure. They are at the forefront of memory subsystem design and high-performance computing, creating innovative solutions that power the next generation of AI processors.

Are you passionate about physical chip design and working through complex challenges? We need you!

We are looking for a STA Engineer to join a highly skilled team developing next-generation AI hardware.

Description:

As a STA Engineer, you will create and verify block and top level timing constraints for multiple blocks and top level designs. Driving timing analysis and closure you will work with cutting-edge technology, collaborating closely with external IP providers, EDA vendors, and silicon/package vendors to deliver high-performance SoCs or SiPs for mass production.

What you will do:

• Working in advanced technology nodes on block level and very large hierarchical designs.
• Working with design teams to develop block and top level constraints.
• Able to analyze constraint quality and constraint coverage for constraints provided by internal and third party vendors, variously at IP, block and top level.
• Ability to quickly and effectively analyze sta results, drive timing closure, generate timing ECO scripts for block and top level physical partitions.
• Work closely with block owners and CAD teams to push timing fixes to blocks.
• Provide expertise and knowledge to the wider design and implementation teams for STA and timing closure.
• Responsibilities include working with junior engineers assisting them closing block level timing in physical design and STA..

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• An ability to setup tool flows if required, including distributed processing task.

Requirements:

• Master’s or PhD degree in Computer Science, Microelectronics, or Physics.
• Proven experience with multiple tapeouts of high-performance SoCs or SiPs.
• Experienced in using revision control systems, preferably GIT.
• Extensive experience using Synopsys Primetime, including DMSA for analyzing multiple scenarios simultaneously.
• High level of TCL proficiency to analyze areas of interest in the timing domain
• Clear understanding and experience in dealing with very large hierarchical designs to include
• Budgeting flows
• Awareness of context in creating block constraints
• Using Hyperscale or other techniques for handling huge designs
• Knowledge of distributed processing / threading options in Primetime
• Experience with PrimeClosure would be an advantage

Why join us:

• Relocation package for you and your family (visa, flight, first month rent, housing assistance).
• Permanent, full-time onsite role in Barcelona, Spain.
• Flexible working hours (9–6, Monday to Friday).
• Work in one of the very few companies in Europe building AI chip infrastructure.
• Small, highly skilled team (147 people) with opportunities for learning and growth.
• Supportive, family-friendly environment with strong relocation assistance.
• Candies, coffee, and free Spanish lessons included! 🇪🇸

How to Apply

If you are passionate about SoC architecture, integration, and AI hardware — and want to be part of a team shaping the future of AI-powered computing — we would love to hear from you!

Join us in building the next generation of AI processing solutions!

By applying to this advertisement, you voluntarily provide your personal data and consent to their processing for the purposes of recruitment. The processing of your personal data is carried out in full compliance with the requirements of Regulation (EU) 2016/679 (General Data Protection Regulation), the Personal Data Protection Act, and all other applicable regulations.

License for the selection of personnel from the Employment Agency No. 3484 of 08.03.2023 and No. 3485 of 08.03.2023 for the EU.