Principal FPGA Design Engineer for High-Precision Timing Systems
Lead the development of high-performance validation and testing platforms for precision timing products. Design and implement scalable FPGA solutions for internal hardware platforms. Collaborate with cross-functional teams to drive system-level requirements.
Key Highlights
Key Responsibilities
Technical Skills Required
Benefits & Perks
Job Description
Principal FPGA Design Engineer โ High-Precision Timing Systems
We are currently partnered with a global leader in MEMS timing solutions, currently shipping billions of devices across networking, mobile, and automotive sectors. The team is looking for a Principal FPGA Design Engineer to lead the development of high-performance validation and testing platforms for precision timing products.
This is a permanent position based in Delft, The Netherlands. (Visa Sponsorship available)
Key Responsibilities:
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- Architect and implement scalable FPGA solutions for internal hardware platforms used in MEMS product validation.
- Lead the full FPGA lifecycle: architecture, RTL design, simulation, synthesis, timing closure, and hardware bring-up.
- Drive system-level requirements and collaborate cross-functionally with CMOS, MEMS, and Test Engineering teams.
- Develop reusable IP blocks and maintain a modular, maintainable FPGA infrastructure.
- Provide technical leadership and mentorship to junior engineers while influencing strategic program direction.
- Act as the technical liaison between engineering and operations to ensure seamless hardware integration.
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Key Requirements:
- MS in Electrical Engineering, Computer Engineering, or a related field.
- 10+ years of hands-on experience in FPGA architecture and development (Xilinx, Intel/Altera).
- Deep expertise in Verilog/VHDL, simulation tools (ModelSim, Vivado), and scripting (Python, TCL).
- Proven track record in designing systems with low jitter, low phase noise, and high signal fidelity.
- Strong knowledge of timing analysis, clock domain crossing, and high-speed interfaces (PCIe, DDR, SERDES).
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Keywords: Principal FPGA Engineer / FPGA Architect / RTL Design / SystemVerilog / Xilinx / Vivado / Low Phase Noise / Low Jitter / Timing Analysis / PCIe / SERDES / MEMS / Signal Integrity / Python / TCL / Hardware Validation
If you are interested in this Principal FPGA Design Engineer position, please send a copy of your CV to ts@eu-recruit.com
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