Senior RTL Design Engineer / Digital IC Engineer (AI Hardware)

IC Resources France
Visa Sponsorship Relocation
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AI Summary

Join a deep-tech startup designing next-generation AI processors in Paris. Work on complex SoCs, microarchitecture, and advanced compute problems. Require 5+ years of RTL design experience with Verilog/SystemVerilog.

Key Highlights
Design advanced processors at the intersection of semiconductors, AI, and photonics
Work on challenging compute problems with a small, close-knit team
Influence microarchitecture and digital design
Key Responsibilities
Design block-level and top-level RTL
Work on complex SoCs including components such as DSP, DDR/LPDDR/HBM, or PCIe
Familiarize with AMBA protocols including AXI, AXI-Stream, ACE, ACE-Lite, APB, and AHB
Experience with logic synthesis, DFT (Design for Test), and physical awareness (PPA)
Technical Skills Required
RTL Design Verilog SystemVerilog SoC Design DSP DDR LPDDR HBM PCIe AMBA Protocols AXI AXI-Stream ACE ACE-Lite APB AHB Logic Synthesis DFT PPA Tcl Perl Python
Benefits & Perks
Visa sponsorship
Relocation support
Nice to Have
Scripting experience in Tcl, Perl, or Python
Strong understanding of SoC integration and high-performance digital systems

Job Description


I’m working with a deep-tech startup hiring a Senior RTL Design Engineer / Digital IC Engineer in Paris. The company is building next-generation AI hardware and is looking for engineers with strong experience in RTL design, microarchitecture, and complex SoC development.

This is an opportunity to join an early-stage team designing advanced processors at the intersection of semiconductors, AI, and photonics, with engineers working close to architecture on challenging compute problems.

Key requirements

  • 5+ years of experience in Digital IC Design or RTL Design
  • Strong experience with Verilog / SystemVerilog
  • Experience designing block-level and top-level RTL
  • Background working on complex SoCs including components such as DSP, DDR / LPDDR / HBM, or PCIe
  • Familiarity with AMBA protocols including AXI, AXI-Stream, ACE, ACE-Lite, APB, and AHB
  • Experience with logic synthesis, DFT (Design for Test), and physical awareness (PPA)

Additional Skills

  • Scripting experience in Tcl, Perl, or Python
  • Strong understanding of SoC integration and high-performance digital systems

Why this role

  • Work on next-generation AI processor architectures
  • Join a small team solving complex AI compute challenges
  • Opportunity to influence microarchitecture and digital design
  • Visa sponsorship and relocation support available

If you’re a Senior RTL Engineer, Digital IC Designer, or SoC Design Engineer interested in advanced AI hardware development, this could be a great opportunity.

For more information, contact Steph Hutchinson.

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