Senior DFT Engineer

Location: Austin, TX (On-site, 5 days/week)

Employment Type: Full-time

Visa Sponsorship: H1-B Sponsorship Available

About The Position

We are seeking an experienced DFT Engineer to join an exciting, well-funded semiconductor start-up working on next-generation SoCs and complex digital and mixed-signal chips.

In this role, you will collaborate closely with backend, VLSI, verification, and analog teams and will be fully responsible for defining, implementing, and deploying advanced Design-for-Test (DFT) methodologies. You will contribute to silicon test strategies, scan architecture, BIST implementation, and overall test quality for cutting-edge silicon products.

Key Responsibilities

• Define and implement SoC DFT strategy and architecture (Scan, ATPG, MBIST, compression).
• Perform scan insertion, compression, hierarchical DFT implementation, and BIST insertion flows
• Insert and integrate DFT logic including boundary scan, scan chains, compression logic, TAP controller, clock control blocks, and other DFT IPs
• Integrate MBIST logic and test controllers across hierarchical designs
• Debug DFT design rule checks and apply fixes to ensure high test coverage and quality
• Support silicon bring-up, debug, and validation of DFT features on ATE
• Debug ATPG and compressed ATPG patterns, MBIST, and JTAG issues
• Work on test plans for analog and mixed-signal IPs

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• Perform fault modeling and coverage analysis
• Document DFT architecture, methodology, and processes
• Collaborate cross-functionally with design, verification, and physical implementation teams
  
  

Mandatory Requirements

• Minimum 5+ years of hands-on experience as a DFT Engineer
• Strong experience in:
• Scan insertion and scan synthesis
• Compression techniques
• Hierarchical DFT architecture and implementation
• BIST insertion flows (Logic BIST, MBIST)
• TAP controller and boundary scan
• Tessent and/or Modus scripting and implementation

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• Experience in DFT specification, architecture definition, insertion, and analysis
• Experience with silicon bring-up, validation, and debug
• Strong experience in ASIC DFT flows including synthesis, simulation, and verification
• Must have current, recent DFT engineering experience
• Stable work history (No job hoppers or career breaks)
• Must be willing to work on-site in Austin, TX (5 days/week)
• Must be eligible to work in the U.S. (H1-B sponsorship available)
  

Note: DFT Test Engineers are not suitable for this role.

Preferred Qualifications

• Master’s degree in Electrical Engineering or related field
• Experience with IP integration (memories, TAP, MBIST, test controllers)
• Experience with industry-standard EDA tools, including:
• Tessent
• Modus

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• Experience debugging ATPG, compressed ATPG, MBIST, and JTAG issues
• Strong understanding of fault modeling techniques
• Experience working on complex SoC and mixed-signal designs
• Excellent analytical, problem-solving, communication, and documentation skills
  

Why Join Us

• Work with a fast-growing, well-funded semiconductor start-up
• Opportunity to contribute to next-generation SoC development
• H1-B visa sponsorship available
• Work with advanced DFT methodologies and cutting-edge technologies
• Highly collaborative and technically strong engineering team