Senior DFx Engineer (GPU/System Interconnect IP) - Samsung Semiconductor
Relocation
AI Summary
Samsung Semiconductor is seeking a seasoned DFx Engineer to define, implement, and debug DFT scan architecture for high-performance computing IP (GPU, system interconnect) in bleeding-edge processes. This role involves close collaboration with cross-functional teams to ensure high test coverage, minimize test time, and resolve silicon issues. The position is based in Austin, TX.
Key Highlights
Responsible for the entire DFx scan architecture lifecycle, from definition to silicon debug.
Works on IP-level projects (GPU, system interconnect) in advanced process nodes.
Requires strong collaboration with SOC, Product/Test Engineering, RTL, STA, and PD teams.
Focuses on improving test coverage, minimizing test time, and enhancing execution efficiency.
Requires strong post-silicon debugging skills for test-escapes and yield loss issues.
Technical Skills Required
Benefits & Perks
Base pay range: $144,345 - $223,735
Exempt position (not eligible for overtime)
Medical, dental, vision, life insurance
401(k)
Free onsite lunch
Employee purchase program
Tuition assistance (after 6 months)
Paid time off
Student loan program
Wellness incentives
MBO bonus compensation
Potential for long-term incentive plan
Relocation assistance
Job Description
Position Summary
Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us!
Role And Responsibilities
As a seasoned DFx engineer, you will be involved across the entire spectrum of activities all the way from defining the DFT scan architecture through implementation and culminating in pattern generation including silicon debug. You will be working on IP-level projects (GPU, system interconnect) in bleeding-edge processes that continually drive high test-coverage requirements. This position is local to Austin, TX only.
- You understand SOC requirements and project milestones to help define a DFT architecture which optimally balances between coverage, test-time, and execution.
- You create a detailed implementation spec which documents details of the architecture including SOC-level interface, clock design, and support of various test/debug modes.
- You close on the spec with stakeholders including DFX / RTL / SOC / STA / PD teams.
- You implement DFT scan: RTL creation, LINT, timing-constraints, ATPG and simulation. Benchmark test-coverage and test-time to ensure that they meet expectations.
- You drive towards continuing DFX excellence: improving test-coverage, minimizing test-time, and exploring tools / methods that improve execution efficiency.
- You build strong collaboration with SOC and Product/Test Engineering teams to quickly resolve any silicon issues including test-escapes and yield loss.
- 10+ years of experience with a Bachelor’s degree in Computer Science/Computer Engineering/relevant technical field, or 8+ years of experience with a Master’s degree, or 6+ years of experience with a PhD
- 10+ years of DFx expertise encompassing multiple tapeouts for digital IP (CPU / GPU) and/or SOC projects
- Demonstrated ability to architect DFT solutions from scratch on at least 1 project, and to create detailed specifications that can be used as a blueprint for implementation.
- Detailed understanding of test-coverage requirements across various scan modes especially as they pertain to bleeding-edge process nodes.
- Strong familiarity with RTL coding & STA with working knowledge of Physical Design
- Familiarity with multi-voltage and multi-clocking domain implementation is a plus.
- Exposure to advanced approaches including hierarchical DFT and streaming fabric.
- Strong post-silicon experience as it relates to debugging silicon behavior and test-escape issues. Is able to solve difficult problems with creative solutions or analysis.
- Crisp written and oral communication skills including working with global stakeholders
- Thrives in fast-paced environment: i.e. yearly project tapeouts
We’re strengthening our team of talented individuals with diverse skill sets to build a technology roadmap and deliver market-leading GPU. Our Xclipse GPU is the first mobile GPU with ray tracing technology that enables console-level graphic for Samsung Galaxy smartphones. With architecture scalability at the frontier of our design focus, our performance- and power-optimized IP solution gets integrated into complex semiconductor products, aiming to reach multiple market segments.
Our Physical Design group is part of the larger Design Implementation team at SARC/ACL. The fast-paced environment here provides us opportunities to learn different areas of design implementation and diversifying our technical expertise. We take pride in our highly collaborative team culture and feel supported by our leadership to explore new ideas and bring them to reality everyday. We believe in connecting your area of expertise with the right level and functional discipline that can empower you to grow.
Total Rewards
At Samsung – SARC/ACL, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $144,345 and $223,735. Your actual base pay will depend on variables that may include your education skills, qualifications, experience, and work location. This is an exempt position, which is not eligible for overtime pay under the Fair Labor Standards Act (FLSA).
Samsung employees have access to benefits including: medical, dental, vision, life insurance, 401(k), free onsite lunch, employee purchase program, tuition assistance (after 6 months), paid time off, student loan program, wellness incentives, and many more. In addition, regular full-time employees (salaried or hourly) are eligible for MBO bonus compensation, based on company, division, and individual performance.
Additionally, this role might be eligible to participate in long term incentive plan and relocation.
U.S. Export Control
This position requires the ability to access information subject to U.S. export control restrictions. Applicants must have the ability to access export-controlled information or be eligible to receive a government authorization to access export-controlled information.
Trade Secrets
By submitting an application, you [applicant] agree[s] not to disclose to Samsung, or induce Samsung to use, any confidential or proprietary information (including trade secrets) belonging to any current or previous employer or other person or entity.
#SARC
- Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.
- Samsung Electronics America, Inc. and its subsidiaries are committed to employing a diverse workforce, and provide Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.