Senior DSP Algorithms Engineer for Optical Communications
Visa Sponsorship
Relocation
AI Summary
We are seeking a senior-level DSP Algorithms Engineer to own system-level performance verification of advanced coherent optical DSP prior to silicon tape-out. This is a problem-centric, high-impact individual contributor role focused on breaking designs before it is too late to fix them.
Key Highlights
System-Level DSP Verification & Stress Testing
Optical Channel & Impairment Modeling
Algorithm-Aware Verification
Technical Skills Required
Benefits & Perks
H1-B Sponsorship Available
Equity: Yes (discussed post-selection)
Relocation: Depends
Job Description
Location: Austin, TX (On-site, 5 days/week – Mandatory)
Employment Type: Full-time
Visa Status: H1-B Sponsorship Available | USC / GC Welcome
Interview Process: 3 Rounds | ~2 Weeks
Relocation: Depends
Equity: Yes (discussed post-selection)
Role Overview
We are seeking a senior-level DSP Algorithms Engineer to own system-level performance verification of advanced coherent optical DSP prior to silicon tape-out.
This is a problem-centric, high-impact individual contributor role focused on breaking designs before it is too late to fix them. The engineer will act as the final technical line of defense against latent algorithmic and system-level issues by stressing DSP designs under realistic and worst-case optical scenarios.
This role is not tool-driven, not QA-focused, and not a ramp-up position—it requires deep, hands-on optical DSP expertise from day one.
Key Responsibilities
System-Level DSP Verification & Stress Testing
- Own end-to-end system-level performance verification across the Tx → fiber → Rx signal chain.
- Design and execute aggressive stress tests, corner cases, and adversarial scenarios to expose algorithmic weaknesses prior to tape-out.
- Focus on robustness validation and bug discovery, not basic functional or feature validation.
- Build and maintain realistic optical channel models, including fiber propagation effects and physical impairments.
- Model impairments such as dispersion, non-linearities, noise, and laser-related effects.
- Translate real-world optical behavior into actionable system-level test scenarios.
- Continuously refine models to reflect worst-case and edge-case deployment conditions.
- Leverage deep DSP algorithm knowledge to intentionally attack known weak points.
- Collaborate closely with DSP algorithm designers to:
- Define performance metrics, acceptance criteria, and failure thresholds
- Interpret failures in the context of algorithmic intent and system trade-offs
- Drive root-cause analysis and corrective action recommendations
- Develop and maintain flexible system-level test frameworks (MATLAB, C/C++, Python, SystemC, or equivalent).
- Automate regression testing and performance analysis to enable rapid iteration.
- Produce clear documentation covering:
- Test methodology and assumptions
- Coverage gaps
- Performance trends and risk areas
- Operate as a self-directed individual contributor within a globally distributed team.
- Serve as a domain expert, contributing deep technical knowledge rather than learning fundamentals on the job.
- Deep expertise in coherent optical communications DSP, with hands-on experience in real optical systems (expertise, not exposure).
- Proven background in DSP algorithm development and system-level verification, preferably in pre-silicon environments.
- Strong understanding of:
- Optical fiber channel behavior and physical impairments
- Coherent receiver architectures and DSP signal processing chains
- Extensive experience with DSP simulation and modeling using:
- MATLAB, C/C++, Python, SystemC, or equivalent
- Ability to independently define, execute, and interpret complex verification strategies.
- Bachelor’s, Master’s, or PhD in Electrical Engineering or related field (degree level secondary to demonstrated expertise).
- Experience in commercial/industrial environments (not purely academic research).
- Ability to work on-site in Austin, TX five days a week (mandatory).
- RTL-level understanding or familiarity with hardware implementation flows.
- Experience with analog front-end (AFE) behavior and DSP interaction.
- Exposure to:
- Fixed-point modeling
- ASIC / DSP implementation considerations
- FEC schemes (LDPC, RS, OFEC)
- Mixed-signal effects such as jitter, PLL, and CDR behavior